Method of Forming a Metal Line and Method of Manufacturing a Display Substrate by Using the Same

ABSTRACT

In a method of forming a metal line and a method of manufacturing a display substrate, a channel layer and a metal layer are successively formed on a base substrate. A photoresist pattern is formed in a wiring area. The metal layer is etched by using the photoresist pattern to form a metal line. The photoresist pattern is removed by a predetermined thickness to form a residual photoresist pattern on the metal line. The channel layer is etched by using the metal line to form an undercut under the metal line. The protruding portion of the metal line is removed by using the residual photoresist pattern. The protruding portion relatively protrudes by formation of the undercut. Thus, an aperture ratio is increased, an afterimage is prevented, and the display quality is improved.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Korean Patent Application No.2006-36745 filed on Apr. 24, 2006, the contents of which are hereinincorporated by reference in their entireties.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to a display substrate, and moreparticularly, to a method of forming a metal line and a method ofmanufacturing a display substrate by using the method of forming a metalline.

2. Discussion of the Related Art

Generally, a liquid crystal display (LCD) device includes a displaysubstrate and a counter substrate coupled to the display substrate toreceive a liquid crystal layer. The display substrate has gate lines,source lines crossing the gate lines, switching elements connected tothe gate and source lines, and pixel electrodes connected to theswitching elements. Each switching element includes a gate electrodeextending from the gate lines, a channel insulated from and overlappedwith the gate electrode, a source electrode formed from the source linesand electrically connected to the channel, and a drain electrode spacedapart from the source electrode and electrically connected to thechannel.

Masks are employed in manufacturing the display substrate. In order toreduce manufacturing time and cost the number of the masks needed tomanufacture the display substrate is minimized. For example, a five-maskprocess employs one mask during each of a gate metal patterning process,a channel patterning process, a source metal patterning process, acontact portion patterning process, and a pixel electrode patterningprocess, and thus a total of five masks may be employed. A four-maskprocess may be similar to the five-mask process described above howevera single mask is used during both the channel patterning process and thesource metal patterning process, and thus a total of four masks may beemployed.

In display substrates manufactured by, the four-mask process, a sourcemetal pattern and a channel pattern are patterned by using one mask.Therefore, the channel pattern is formed more protrusive than the sourcemetal pattern. Having a more protrusive channel pattern reduces anaperture ratio and changes a coupling capacitance between the channelpattern and the pixel electrode. This may be due to a light leakedcurrent, thereby changing waterfall effect noise and drivingcharacteristics of the switching element to incur some problems such asan afterimage.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a method of forming a metalline capable of improving display quality.

Embodiments of the present invention also provide a method ofmanufacturing a display substrate by using the above-mentioned method.

A method of forming a metal line in accordance with an embodiment of thepresent invention is provided as follows. A channel layer and a metallayer are successively formed on a base substrate. A photoresist patternis formed in a wiring area. The metal layer is etched by using thephotoresist pattern to form a metal line. The photoresist pattern isremoved by a predetermined thickness to form a residual photoresistpattern on the metal line. The channel layer is etched by using themetal line to form an undercut under the metal line. The protrudingportion of the metal line is removed by using the residual photoresistpattern. The formation of the undercut may produce the protrudingportion.

A method of manufacturing a displays substrate in accordance with anembodiment of the present invention is provided as follows. A channellayer and a source metal layer are successively formed on a basesubstrate having a gate line and a gate electrode of a switchingelement. A first photoresist pattern is formed in a source line area anda first area. A second photoresist pattern is formed in a second area. Asource electrode and a drain electrode of the switching element areformed in the first area and a channel portion of the switching elementis formed in the second area. Then, the source metal layer is patternedby using, the first and second photoresist patterns to form an electrodemetal pattern in the first and second areas and to form a source line inthe source line area. A residual photoresist pattern is formed on theelectrode metal pattern of the first area. The first and secondphotoresist patterns are removed by a predetermined thickness to exposethe electrode metal pattern in the second area. The channel layer isetched using the electrode metal pattern and the source line to formundercuts under the electrode metal pattern and the source line. Theelectrode metal pattern is etched in the second area to form the sourceelectrode and the drain electrode. A pixel electrode that iselectrically connected to the drain electrode of the switching elementis formed.

According to the above, a protruding, portion of a channel patterndisposed under a source line, a source electrode and a drain electrodeis removed. As a result, an aperture ratio may be increased, anafterimage may be prevented, and display quality may be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features of the present disclosure will become moreapparent by describing exemplary embodiments thereof with reference tothe accompanying drawings, in which:

FIG. 1 is a plan view illustrating a display substrate according to anexemplary embodiment of the present invention,

FIGS. 2A to 2G are cross-sectional views illustrating a method ofmanufacturing a display substrate according to an exemplary embodimentof the present invention,

FIGS. 3A to 3D are cross-sectional views illustrating a method ofmanufacturing a display substrate according to an exemplary embodimentof the present invention; and

FIGS. 4A to 4F are cross-sectional views illustrating a method ofmanufacturing a display substrate according to an exemplary embodimentof the present invention.

The invention is described more fully hereinafter with reference to theaccompanying drawings, in which embodiments of the invention are shown.This invention may, however be embodied in many different forms andshould not be construed as limited to the embodiments set forth herein.In the drawings, the size and relative sizes of layers and regions maybe exaggerated for clarity.

It will be understood that when an element or layer is referred to asbeing “on,” “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present.

FIG. 1 is a plan view illustrating a display substrate according to anexemplary embodiment of the present invention. Lines I′, II, II′, IIIand III′ are shown.

Referring to FIG. 1, a display substrate includes a plurality of gatelines GL, a plurality of source lines DL, a plurality of switchingelements TFT, a plurality of pixel electrodes PE and a storage line STL.

The gate lines GL extends in a first direction. The gate lines GL mayinclude at least one of a copper (Cu) group metal such as copper andcopper alloy, an aluminum (Al) group metal such as aluminum and aluminumalloy, a molybdenum (Mo) group metal such as molybdenum and molybdenumalloy, chromium (Cr), tantalum (Ta), and titanium (Ti). The gate linesGL may have a single layer structure or a multiple layer structure.

A gate pad portion GP is formed at an end of each gate line GL. The gatepad portion GP includes a first pad pattern (not shown) electricallyconnected to the end of each gate line GL.

The source lines DL extend in a second direction crossing, the firstdirection. The source lines DL may include at least one of a copper (Cu)group metal such as copper and copper alloy, an aluminum (Al) groupmetal such as aluminum and aluminum alloy, a molybdenum (Mo) group metalsuch as molybdenum and molybdenum alloy, chromium (Cr), tantalum (Ta),and titanium (Ti). The source lines DL may have a single layer structureor a multiple layer structure.

A source pad portion DP is formed at an end of each source line DL. Thesource pad portion DP includes a second pad pattern (not shown)electrically connected to the end of each source line DL.

Each switching element TFT is formed on one of a plurality of pixelportions P defined by the gate lines GL and the source lines DL. Eachswitching element TFT includes a gate electrode GE electricallyconnected to the corresponding gate line GL, a source electrode SEelectrically connected to the corresponding source line DL, and a drainelectrode DE spaced apart from the source electrode SE and electricallyconnected to the source electrode SE through a channel portion (notshown).

The pixel electrodes PE are electrically connected to the switchingelements TFT. For example, each pixel electrode PE is electricallyconnected to the drain electrode DE of corresponding switching elementsTFT. The pixel electrode PE may include a transparent and conductivematerial. Examples of the transparent and conductive material include,for example, oxide or nitride containing at least one selected from thegroup of indium (In), tin (Sn) zinc (Zn) aluminum (Al), gallium (Ga),etc.

The storage line STL overlaps the pixel electrode PE and receives acommon voltage. The storage line STL and the pixel electrode PE define astorage capacitor. In an exemplary embodiment, a common type having thestorage line STL is illustrated in FIG. 1. Alternatively, a storage linemay be formed employing a previous gate type. The storage line of thecommon type is independently formed and receives a common voltage. Thestorage line of the previous gate type is connected to a previous gateline, and a gate-off voltage is applied to the previous gate line servesas a common voltage.

FIGS. 2A to 2G are cross-sectional views illustrating a method ofmanufacturing a display substrate according to a first exemplaryembodiment of the present invention.

Referring to FIGS. 1 and 2A, a gate metal layer is deposited on a basesubstrate 101, and the gate metal layer is patterned by using a firstphotoresist pattern (not shown) to form the gate line GL, the gateelectrode GE and the storage line STL. A gate insulation layer 102 isformed on the base substrate 101 having the gate line GL, the gateelectrode GE and the storage line STL. A channel layer 110 is formed onthe gate insulation layer 102. The channel layer 110 includes an activelayer 110 a having successively formed amorphous silicon (a-Si), and anohmic contact layer 110 b having amorphous silicon highly doped with n+ions (n+ a-Si).

Referring to FIGS. 1 and 2B, a source metal layer (not shown) isdeposited on the base substrate 101 having the channel layer 110 and asecond photoresist pattern is formed on the source metal layer. Thesecond photoresist pattern includes a first sub-photoresist pattern PR1,having a length ‘L’, formed in a source electrode area (SEA), a drainelectrode area (DEA) and a source line area DLA and having a firstthickness t1, and a second sub-photoresist pattern PR2 formed in achannel area CHA and having a second thickness t2. The secondsub-photoresist pattern PR2 is patterned by using a slit mask or ahalftone mask to have the second thickness t2 that is thinner than thefirst thickness t1.

The first sub-photoresist pattern PR1 may have an inclined angle θ1 ofmore than or equal to about 60 degrees, for example, 90 degrees. Aninclined angle θ2 of a stepped portion between the first and secondsub-photoresist patterns PR1 and PR2 may be about 60 degrees accordingto the process characteristics. The second thickness t2, may becontrollable. For example, the second thickness t2 is smaller than orequal to about 5000 Å. The source metal layer is wet etched by using thefirst and second sub-photoresist patterns PR1 and PR2 to form anelectrode metal pattern 121 and the source line DL.

Referring to FIGS. 1 and 2C, the first and second sub-photoresistpatterns PR1 and PR2 are partially removed by a predetermined thicknessthrough an etch back process to thereby form a first residualsub-photoresist patterns PR1′ on the electrode metal pattern 121 and thesource line DL. The first residual sub-photoresist patterns PR1′ isformed to expose edge portions ‘a’ of the electrode metal pattern 121and the source line DL, and expose the channel area CHA of the electrodemetal pattern 121. Conditions of the etch back process may be controlledso that the exposed edge portions ‘a’ may have a length of smaller thanor equal to about 0.5 μm.

In an exemplary embodiment, the first residual sub-photoresist patternsPR1′ may be formed to expose the edge portions ‘a’ of the electrodemetal pattern 121 and the source line DL. Alternatively, the firstresidual sub-photoresist patterns PR1′ may be formed to extend to theedge portions ‘a’ of the electrode metal pattern 121 and the source lineDL, and may be formed to partially cover the edge portions ‘a’ of theelectrode metal pattern 121 and the source line DL. For example, alength of the edge portions ‘a’ may be smaller than or equal to about0.5 μm. The channel layer 110 is patterned to form undercuts ‘b’ (referto FIG. 2D), and the protruding channel layer 110 may be removed whenthe undercuts ‘b’ are longer than the edge portions ‘a’. When the edgeportions ‘a’ have a length of more than about 0.5 μm, the undercuts ‘b’may, have a relatively long length.

A decreased amount of a length ‘L’ of the first sub-photoresist patternPR1 may be approximately equal to a decreased amount of the firstthickness t1 of the first sub-photoresist pattern PR1 when the angle ofincline θ1 of the first sub-photoresist pattern PR1 is about 45 degrees.The decreased amount of the length ‘L’ of the first sub-photoresistpattern PR1 may be smaller than the decreased amount of the firstthickness t1 of the first sub-photoresist pattern PR1 when θ1 is morethan 45 degrees. In contrast, the decreased amount of the length ‘L’ ofthe first sub-photoresist pattern PR1 is greater than the decreasedamount of the first thickness t1 of the first sub-photoresist patternPR1 at less than about 45 degrees of the inclined angle θ1 of the firstsub-photoresist pattern PR1. The second photoresist pattern having thefirst and second sub-photoresist patterns PR1 and PR2 is partiallyremoved through an etch back process in consideration of the decreasedamount of the length ‘L’ of the first sub-photoresist pattern PR1 andthe decreased amount of the first thickness t1 of the firstsub-photoresist pattern PR1 at the inclined angle θ1 of the firstsub-photoresist pattern PR1.

For example, in order for the length of the edge portions ‘a’ to beabout equal to or less than 0.5 μm, the inclined angle θ1 of the firstsub-photoresist pattern PR1 may be formed to have a range of about 60degrees to about 90 degrees.

For example, the inclined angle θ1 of the first sub-photoresist patternPR1 is about 45 degrees. In this case, when the first and secondsub-photoresist patterns PR1 and PR2 are removed, a ratio of thedecreased amount of the length ‘L’ of the first sub-photoresist patternPR1 to the decreased amount of the first thickness t1 of the firstsub-photoresist pattern PR1 or the decreased amount of the secondthickness t2 of the second sub-photoresist pattern PR2 may be about 1:1.Thus, when the second thickness t2 of the second sub-photoresist patternPR2 is controlled, the length of the edge portions ‘a’ may also becontrollable. For example, when the second thickness t2 of the secondsub-photoresist pattern PR2 is smaller than or equal to about 5000 Å,the length of the edge portions ‘a’ may be less than or equal to about0.5 μm.

Referring to FIGS. 1 and 2D, the channel layer 110 formed under theelectrode metal pattern 121 and the source line DL is dry etched. Thechannel layer 110 is isotropically dry etched to form the undercuts ‘b’each having a predetermined length under the electrode metal pattern 121and the source line DL.

For example, the channel layer 110 is isotropically dry etched by usingSF₆/Cl₂ gas serving as a base in a plasma etch (“PE”) process. An etchrate of the channel layer 110, for example, an amorphous silicon layer,may be set high, and an amount of over-etching may be increased. Theamount of over-etching represents an amount of additional etching afterthe channel layer 110 is entirely removed and the gate insulation layer102 is first exposed. When the amount of over-etching is increased undera condition of high etch rate of the amorphous silicon layer, the gateinsulation layer 102 positioned under the channel layer 110 is not verywell etched, but the amorphous silicon layer laterally positioned isetched to form the undercuts ‘b’. When SF₆/Cl₂ gas is mixed with O₂ gas,a surface of the amorphous silicon layer is oxidized to SiOx, and thusetch rate of the amorphous silicon layer is reduced. Thus, SF₆/Cl₂ gasmay include lower than about 20 percent of O₂ gas.

For example, a first channel pattern 111 is formed under the electrodemetal pattern 121. The first channel pattern 111 is over-etched by about0.5 μm to about 1 μm from an edge of the electrode metal pattern 121. Asecond channel pattern 113 is formed under the source line DL. Thesecond channel pattern 113 is over-etched by about 0.5 μm to about 1 μmfrom an edge of the source line DL. In order to remove protrudingportions of the first and second channel patterns 111 and 113, thelength of the undercuts ‘b’ formed under the electrode metal pattern 121may be greater than or equal to the length of the edge portions ‘a’.

Referring to FIGS. 1 and 2E, due to the undercuts ‘b’, the electrodemetal pattern 121 has a first protruding portion 131 that is moreprotrusive than the first channel pattern 111, and the source line DLhas a second protruding portion 133 that is more protrusive than thesecond channel pattern 113.

The exposed portion of the electrode metal pattern 121 of the channelarea CHA is removed through a dry etch process by using the firstresidual sub-photoresist pattern PR1′ to thereby forms the sourceelectrode SE and the drain electrode DE of the switching element TFT.Since the first and second protruding portions 131 and 133 are removed,the source electrode SE, the drain electrode DE and the source line DLhas an etched surface that is substantially the same or minutely moreprotrusive than the first and second channel patterns 111 and 113,respectively. For example, the source electrode SE, the drain electrodeDE and the source line DL each have an etched surface that issubstantially the same as the first and second channel patterns 111 and113, respectively.

Through the dry etch process, when the electrode metal pattern 121 isremoved, only the first and second protruding portions 131 and 133 areremoved. In contrast, in a wet etch process, an etchant permeatesbetween the first and second protruding portions 131 and 133 and thefirst and second channel patterns 111 and 113, to thereby etch the firstand second protruding portions 131 and 133, and thus the first andsecond protruding portions 131 and 133 may remain.

In comparison with a conventional four mask process, a protrusivechannel pattern is not formed under the source electrode SE, the drainelectrode DE and the source line DL. Thus, aperture ratio reduction,afterimage defect, display quality, deterioration, etc. may be preventedin embodiments of the present invention.

Then, a portion of the ohmic contact layer 110 a, which is exposed bythe source electrode SE and the drain electrode DE serving as a mask, isremoved to form a channel portion CH of the switching element TFT.

Referring to FIGS. 1 and 2F, a protective insulation layer 103 is formedon the base substrate 101 having the channel portion CH. Then, a thirdphotoresist pattern (not shown) is formed on the base substrate 101having the protective insulation layer 103. A first contact portion C1,a second contact portion C2 and a third contact portion C3 is formed byusing the third photoresist pattern. The first contact portion C1exposes the drain electrode DE, the second contact portion C2 exposes anend portion of the gate line GL, and the third contact portion C3exposes an end portion of the source line DL.

Referring to FIGS. 1 and 2G, a transparent electrode layer (not shown)is formed on the base substrate 101 having the first, second and thirdcontact portions C1, C2 and C3. The transparent electrode layer makescontact with the drain electrode DE, the end portion of the gate line GLand the end portion of the source line DL through the first, second andthird contact portions C1, C2 and C3, respectively.

The transparent electrode layer is patterned by using a fourthphotoresist pattern (not shown) to form a pixel electrode PEelectrically connected to the drain electrode DE, a first pad pattern141 electrically connected to the end portion of the gate line GL and asecond pad pattern 142 electrically connected to the end portion of thesource line DL.

FIGS. 3A to 3D are cross-sectional views illustrating a method ofmanufacturing a display substrate according an exemplary embodiment ofthe present invention.

A gate line GL, a gate electrode GE and a storage line STL are formed byusing the first photoresist pattern as described above. The sourceelectrode SE, the drain electrode DE and the source line DL are formedby using the second photoresist pattern as described above. These steps,which are illustrated in the method of manufacturing a display substrateaccording to the exemplary embodiment of the present invention describedin connection with FIGS. 2A-2G, are substantially the same as the methodof manufacturing a display substrate according to the exemplaryembodiment of the present invention described in connection with FIGS.3A-3D. Hereinafter, processes after forming the protective insulationlayer 103 on the base substrate 101 having the source electrode SE, thedrain electrode DE and the source line DL will be described in detailwith reference to the accompanying drawings, FIGS. 3A to 3D. The samereference numerals will be used to refer to the same parts.

Referring to FIGS. 1 and 3A, a third photoresist pattern is formed onthe base substrate 101 having the protective insulation layer 103. Thethird photoresist pattern includes a third sub-photoresist pattern PR3formed in a switching element area SWA having the switching element TFTand a wiring area (not shown), having the gate line GL and the sourceline DL, and a fourth sub-photoresist pattern PR4 formed in a storagearea STA having the storage line STL. The third and fourthsub-photoresist patterns PR3 and PR4 have a third thickness t3 and afourth thickness t4, respectively.

The fourth sub-photoresist pattern PR4 is patterned by using a slit maskor a halftone mask to have the fourth thickness t4 that is thinner thanthe third thickness t3.

The third photoresist pattern having the third and fourthsub-photoresist patterns PR3 aid PR4 is not formed in a first contactarea CA1 corresponding to an end portion of the drain electrode DE, asecond contact area CA2 corresponding to an end portion of the gate lineGL, and a third contact area CA3 corresponding to an end portion of thesource line DL. Also, the third photoresist pattern having the third andfourth sub-photoresist patterns PR3 and PR4 is not formed in a pixelelectrode area PEA except for the storage area STA.

Referring to FIGS. 1 and 3B, the gate insulation layer 102 and theprotective insulation layer 103 are removed through a first dry etchprocess by using the third photoresist pattern and by having the thirdand fourth sub-photoresist patterns PR3 and PR4 serve as a mask. Thus, aportion of the base substrate 101 corresponding to the pixel electrodearea PEA except for the storage area STA is exposed. An end portion ofthe drain electrode DE, an end portion of the gate line GL, and an endportion of the source line DL are also exposed.

Then, the exposed end portion of the drain electrode DE, the exposed endportion of the gate line GL, and the exposed end portion of the sourceline DL are etched through a second dry etch process, to thereby form afirst contact portion C1, a second contact portion C2 and a thirdcontact portion C3.

Referring to FIGS. 1 and 3C, the third photoresist pattern having thethird and fourth sub-photoresist patterns PR3 and PR4 is partiallyremoved through an etch back process. The fourth sub-photoresist patternPR4 is removed to expose the protective insulation layer 103 over thestorage line STL, and the third sub-photoresist pattern PR3 is removedby a predetermined thickness to form a second residual sub-photoresistpattern PR3′ in the switching element area SWA and the wiring area (notshown).

A transparent electrode layer 140 is formed on the base substrate 101having the second residual sub-photoresist pattern PR3′. The transparentelectrode layer 140 makes contact with a side portion of the drainelectrode DE by the first contact portion C1, a side portion of the gateline GL by the second contact portion C2, and a side portion of thesource line DL by the third contact portion C3.

Referring to FIGS. 1 and 3D, the second residual sub-photoresist patternPR3′ is removed, for example, through a stripping process. Thus, thetransparent electrode layer 140 is patterned to form a pixel electrodePE electrically connected to the drain electrode DE, a first pad pattern141 electrically connected to the gate line GL and a second pad pattern142 electrically connected to the source line DL.

FIGS. 4A to 4F are cross-sectional views illustrating a method ofmanufacturing a display substrate according to an exemplary embodimentof the present invention.

The method of manufacturing a display substrate according to the presentembodiment of the present invention includes process steps that aredescribed above with reference to the method of manufacturing a displaysubstrate according to the exemplary embodiment of the present inventiondescribed in connection with FIGS. 2A-2G except for further includingforming a cover metal pattern to cover the storage line STL during theprocess of forming the source electrode SE, the drain electrode DE andthe source line DL, for example, by using the second photoresistpattern. The method of manufacturing a display substrate according tothe present embodiment of the present invention further includes forminga protective insulation layer and a transparent electrode layer by usinga third photoresist pattern, which is similar to the method ofmanufacturing a display substrate according to an exemplary embodimentof the present invention. Hereinafter, the method of manufacturing adisplay substrate according to the third exemplary embodiment of thepresent invention will be described with reference to the accompanyingdrawings, FIGS. 4A to 4D. The same reference numerals will be used torefer to the same parts.

Referring to FIGS. 1 and 4A, a gate insulation layer 102 and a channellayer 110 is successively formed on the base substrate 101 having thegate line GL, the gate electrode GE and the storage line STL. A sourcemetal layer (not shown) is formed on the base substrate 101 having thechannel layer 110. A second photoresist pattern including a firstsub-photoresist pattern PR1 and a second sub-photoresist pattern PR2 isformed on the source metal layer. The first sub-photoresist pattern PR1is formed in the source electrode area SEA, the drain electrode areaDEA, the storage area STA and the source line area DLA, and the secondsub-photoresist pattern PR2 is formed in the channel area CHA.

Referring to FIGS. 1 and 4B, the first and second sub-photoresistpatters PR1 and PR2 are partially removed by a predetermined thicknessthrough an etch back process to thereby expose the electrode metalpattern 121 and form first residual sub-photoresist patterns PR1′ on theelectrode metal pattern 121, the source line DL and a cover electrodepattern 123. The first residual sub-photoresist patterns PR1′ exposeedge portions ‘a’ of the electrode metal pattern 121, the source line DLand the cover electrode pattern 123.

Referring to FIGS. 1 and 4C, the channel layer 110 is etched to formfirst, second and third channel patterns 111, 113 and 115 (respectively)having undercuts ‘b’ formed under the electrode metal pattern 121, thesource line DL and the cover electrode pattern 123 respectively.

Referring to FIGS. 1 and 4D, due to the undercuts ‘b’ the electrodemetal pattern 121, the source line DL and the cover electrode pattern123 have first, second, and third protruding portions 131, 133 and 135(respectively) that are more protrusive than the first, second and thirdchannel patterns 111, 113 and 115, respectively.

The source electrode SE and the drain electrode DE are formed through anetch process by using the first residual sub-photoresist pattern PR1′.The first, second and third protruding portions 131, 133 and 135(respectively) are removed to form the electrode metal pattern 121, thesource line DL and the cover electrode pattern 123 having an etchedsurface that is substantially the same as the first, second and thirdchannel patterns 111, 113 and 115, respectively.

Referring to FIGS. 1 and 4E, a protective insulation layer 103 is formedon the base substrate 101 having the source electrode SE, the drainelectrode DE, the source line DL and the cover electrode pattern 123. Athird photoresist pattern PR3 is formed on the base substrate 101 havingthe protective insulation layer 103. The third photoresist pattern PR3is formed in a switching element area SWA having the switching elementTFT and a wiring area (not shown) having the gate line GL and the sourceline DL.

The third photoresist pattern PR3 is not formed in a first contact areaCA1 corresponding to an end portion of the drain electrode DE, a secondcontact area CA2 corresponding to an end portion of the gate line GL, athird contact area CA3 corresponding to an end portion of the sourceline DL or a pixel electrode area PEA having the pixel electrode PE.

The gate insulation layer 102 and the protective insulation layer 103are removed through a first etch process by using the third photoresistpattern PR3 as a mask. Then, the end portion of the drain electrode DE,the end portion of the gate line GL and the end portion of the sourceline DL are etched through a second etch process to form first, secondand third contact portions C1, C2 and C3 (respectively). The cover metalpattern 123 is removed through the second etch process to expose thethird channel pattern 115 over the storage line STL.

Referring to FIGS. 1 and 4F, a transparent electrode layer (not shown)is formed on the base substrate 101 having a first, second and thirdcontact portions C1, C2 and C3 (respectively). Then, the thirdphotoresist pattern PR3 is removed through a stripping process. Thus,the transparent electrode layer is patterned to form the pixel electrodePE electrically connected to the drain electrode DE, a first pad pattern141 electrically connected to the gate line GL and a second pad pattern142 electrically connected to the source line DL.

According to embodiments of the present invention, in a process offorming a source line by using one mask with respect to a source metallayer and a channel layer formed under the source metal layer, a channellayer that is more protrusive than the source line is removed. Thus, thedisplay quality may be improved.

For example, a protruding portion of the channel layer under the sourceline is removed to improve an aperture ratio and simplify a minutewiring process. A coupling capacitance is not generated between a pixelelectrode and the channel layer to thereby remove a waterfall noise andprevent an afterimage defect.

Although exemplary embodiments of the present invention have beendescribed, it is understood that the present invention should not belimited to these exemplary embodiments but various changes andmodifications can be made by one ordinary skilled in the art within thespirit and scope of the present invention.

1. A method of forming a metal line, comprising: forming a channel layeron a base substrate; forming a metal layer on the formed channel layer;forming a photoresist pattern in a wiring area of the metal layer;etching the metal layer by using the photoresist pattern to form a metalline; removing a predetermined thickness of the photoresist pattern toform a residual photoresist pattern on the metal line; etching thechannel layer by using the metal line to form an undercut under themetal line and to cause a portion of the metal line to protrude relativeto the channel layer; and removing the protruding portion of the metalline by using the residual photoresist pattern.
 2. The method of claim1, wherein the channel layer is isotropically dry etched.
 3. The methodof claim 1, wherein the undercut has a length of about 0.5 μm to about 1μm.
 4. The method of claim 1, wherein the protruding portion of themetal line is removed through a dry etching process.
 5. The method ofclaim 1, wherein the residual photoresist pattern is formed on the metalline to expose an edge portion of the metal line, and a length of theundercut is longer than or equal to a length of the exposed edgeportion.
 6. The method of claim 5, wherein the exposed edge portion hasa length of less than or equal to about 0.5 μm.
 7. The method of claim5, wherein the undercut has a length of about 0.5 μm to about 1 μm. 8.The method of claim 5, wherein the protruding portion of the metal lineis removed through a dry etching process.
 9. The method of claim 1,wherein the residual photoresist pattern is formed on the metal line toexpose an edge portion of the metal line, and wherein the exposed edgeportion has a length of less than or equal to about 0.5 μm, and theundercut has a length of about 0.5 μm to about 1 μm.
 10. A method ofmanufacturing a display substrate, comprising: forming a channel layeron a base substrate, the substrate having a gate line and a gateelectrode of a switching element; forming a source metal layer on theformed channel layer; forming a first photoresist pattern on the sourcemetal layer in a source line area and a first area, wherein a sourceelectrode and a drain electrode of the switching element is formed inthe first area; forming a second photoresist pattern on the source metallayer in a second area, wherein a channel portion of the switchingelement is formed in the second area; patterning the source metal layerby using the first and second photoresist patterns to form an electrodemetal pattern in the first and second areas and a source line in thesource line area; forming a residual photoresist pattern on theelectrode metal pattern of the first area, and removing the first andsecond photoresist patterns by a predetermined thickness to expose theelectrode metal pattern in the second area; etching the channel layer byusing the electrode metal pattern and the source line to form undercutsunder the electrode metal pattern and the source line; etching theelectrode metal pattern in the second area to form the source electrodeand the drain electrode, and forming a pixel electrode electricallyconnected to the drain electrode of the switching element.
 11. Themethod of claim 10, wherein the first photoresist pattern has aninclined angle of about 60 degrees to about 90 degrees with respect tothe base substrate.
 12. The method of claim 11, wherein the secondphotoresist pattern has a thickness of about 5000 Å.
 13. The method ofclaim 10, wherein the residual photoresist pattern is formed on theelectrode metal pattern and the source line to expose edge portions ofthe electrode metal pattern and the source line, and a length of theundercuts is greater than or equal to a length of the edge portions. 14.The method of claim 10, wherein the channel layer is isotropically dryetched.
 15. The method of claim 10, further comprising removingprotruding portions of the electrode metal pattern and the source lineby using the residual photoresist pattern, the protruding portionsprotruding in relation to the undercuts.
 16. The method of claim 15,wherein the protruding portion of the electrode metal pattern is removedthrough a dry etching process.
 17. The method of claim 10, whereinforming the source electrode and the drain electrode comprises selectivethe channel layer by using the source electrode and the drain electrodeto form the channel portion.
 18. The method of claim 10, wherein formingthe pixel electrode comprises: forming a protective insulation layer onthe base substrate having the switching element; removing the protectiveinsulation layer by using a third photoresist pattern to form a contactportion corresponding to the drain electrode; forming a transparentelectrode layer making contact with the drain electrode through thecontact portion; and patterning the transparent electrode layer by usinga fourth photoresist pattern to form the pixel electrode.
 19. The methodof claim 10, further comprising forming the gate line, the gateelectrode and a storage line on the base substrate.
 20. The method ofclaim 19, wherein forming the pixel electrode comprises: forming aprotective insulation layer on the base substrate having the switchingelement; forming a third photoresist pattern on areas having theswitching element, the gate line and the source line; removing a portionof the protective insulation layer corresponding to an area that has thepixel electrode and includes an end portion of the drain electrode byusing the third photoresist pattern; forming a transparent electrodelayer on the base substrate having a remaining portion of the protectiveinsulation layer; and removing the third photoresist pattern andpatterning the transparent electrode layer to form the pixel electrodeto make contact with the end portion of the drain electrode.
 21. Themethod of claim 20, wherein forming the third photoresist patterncomprises forming a forth photoresist pattern that covers the storageline, the fourth photoresist pattern being thinner than the thirdphotoresist pattern.
 22. The method of claim 21, further comprisingremoving the fourth photoresist pattern prior to forming the transparentelectrode layer.
 23. The method of claim 20, further comprisingsimultaneously: forming a cover metal pattern covering the storage linewith the source line; and removing the cover metal pattern with theprotective insulation layer.
 24. The method of claim 10, wherein theresidual photoresist pattern is formed on the metal pattern and thesource line to expose edge portions of the electrode metal pattern andthe metal line, and wherein each of the exposed edge portions has alength of less than or equal to about 0.5 μm, and each of the undercutshas a length of about 0.5 μm to about 1 μm.